摘要
基于FPGA的可编程片上系统(SoPC)以其设计灵活、可裁剪、软硬件可在线编程等特点和优势,成为嵌入式系统设计,乃至电子领域发展的一个重要方向。用户IP核的设计是SoPC设计的重要组成部分,介绍了通信系统的SoPC系统架构,提出利用IPIF将用户IP核挂载到PLB总线上的方法,给出了RLC和物理层接口的IP核的设计与实现。设计中首先把IPIF信号转换成用户逻辑的内部信号,同时对不同速率的接口进行数据缓存,实现流水线传输,从而提高传输速率。
FPGA-based Programmable System on Chip(SoPC)with its flexible design,scalable,hardware and software online programming and other features and advantages,becomes an important direction of the embedded system design,and even the development of electronic.User IP core design is an important part of SoPC design.The paper first briefly introduces the SoPC architecture of communication system,and then makes use of IPIF to mount the user IPcore to the PLB bus,at last gives the design and implementation of RLC and PHY Layer interface IP core.In the design,first transfer the IPIF signals into the user logic internal signal,and then cache data of the interface of different rates,to realize the pipelined transmission and improve the transmission speed.
出处
《电子测量技术》
2010年第7期117-120,124,共5页
Electronic Measurement Technology
基金
福建省重大专项项目资助(2009HZ0003-1)