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基于片上网络的容错通信方法 被引量:2

Fault-Tolerant Communication Method for Network-on-Chip
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摘要 本文提出了一种基于片上网络的容错通信算法。若NoC中出现路由器或者链路故障,将导致NoC不能有效地进行通信。本方案为每个路由器的输出端口配置输出状态寄存器,标识出输出端口所连接的路由器或链路的故障状态,从而建立起一个新的容错模型,在路由时采用新的可重构路由算法避免这些故障的路由器和链路,从而达到保证NoC有效通信的目的。本文在5×52D-Mesh结构上仿真了所提出的方案,统计了数据传输时延,实验结果表明,与现有方案相比,这种方法能够在保证容忍NoC中路由器和链路故障的前提下,获得较低的通信时延。 In this paper,we present a fault-tolerant communication method for network-on-chip.When router or link is failure,NoC can’t effectively communication.In order to solve this problem,we set up the model of fault-tolerance through configuring the status register for the output port of each router which mark the status of router and link which is connected to this router,and use the reconfigurable routing algorithm when routing the data.The proposed method is simulated on the structure which is based on 5×5 2D-Mesh NoC.The experimental results show that this method could reduce the delay of data transmission,which is in the premise of ensuring the fault-tolerance.
出处 《电信科学》 北大核心 2010年第7期55-60,共6页 Telecommunications Science
基金 国家自然科学基金资助项目(No.60876028 No.60633060) 安徽省自然科学基金资助项目(No.090412034) 安徽高校省级自然科学研究重点项目(No.KJ2010A280)
关键词 片上网络 容错模型 可重构路由算法 network on chip model of fault-tolerance reconfigurable routing algorithm
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参考文献11

  • 1Benini L, Mieheli G D. Networks on chips: a new SoC paradigm. IEEE Transactions on Computers, 2002, 35( 1 ): 70-78.
  • 2Daly W J, Towles B. Route packets, not wires: on-chip interconnection networks. In: the 38rd ACM/IEEE Design Automation Conference, Las Vegas, NV, USA, June 2001.
  • 3高明伦,杜高明.NoC:下一代集成电路主流设计技术[J].微电子学,2006,36(4):461-466. 被引量:31
  • 4Zhang Z, Greiner A, Taktak S. A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh network-on-chip. In: the 45rd ACM/IEEE Design Automation Conference, Anaheim, California, USA, June 2008.
  • 5Yong-Bin Kim. Fault tolerant source routing for networkon-chip. In: Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2007, Rome, Italy, Sept 2007.
  • 6张磊,李华伟,李晓维.用于片上网络的容错通信算法[J].计算机辅助设计与图形学学报,2007,19(4):508-514. 被引量:18
  • 7Murali S, Atienza D, Benini L, et al. A multi-path routing strategy with guaranteed in-order packet delivery and fauh-tolerance for networks on chip. In: the 43rd ACM/IEEE Design Automation Conference, July 2006.
  • 8Li M, Zeng Q A, Jone W B. DyXY - a proximity congestionaware deadlock-free dynamic routing method for network on chip. In: the 43rd ACM/IEEE Design Automation Conference, July 2006.
  • 9Xiang D, Zhang Y, Pan Y. Practical deadlock-free fault-tolerant routing in meshes based on the planar network fault model. IEEE Transactions on Computers, 2009, 58(5): 620-633.
  • 10Wu Ning, Ge Fen, Wang Qi. Simulation and performance analysis of network on chip architectures using OPNET. In: the 7th International Conference on ASIC, Guilin, China, October 2007.

二级参考文献27

  • 1ITRS.International Technology Roadmap for Semiconductors[EB/OL].http://public.itrs.net.2003.
  • 2ITRS.International Technology Roadmap for Semiconductors[EB/OL].http://public.itrs.net.1999.
  • 3Tully J,Gordon R,Bruederle S,et al.Hype cycle for semiconductors,2004[R].Gartner research's Technical Report,2004.ID Number:G00120909:2-3.
  • 4Benini L,De Micheli G.Networks on chips:a new SoC paradigm[J].Computer,2002,35(1):70-78.
  • 5Jerraya A,Wolf W,eds.Multiprocessor systems-on-chips[M].San Francisco,Morgan Kaufman / Elsevier,2004.
  • 6Hemani A,Jantsch A,Kumar S,et al.Network on chip:an architecture for billion transistor era[A].Proc IEEE NorChip Conf[C].Turku,Finland.2000.166-173.
  • 7Guerrier P,Grenier A.A generic architecture for on-chip packet-switched interconnections[A].Des Autom and Test in Euro Conf[C].Paris,France.2000.250-256.
  • 8Pham D.The design and implementation of a first-gen-eration CELL processor[A].Int Sol Sta Circ Conf[C].San Francisco,CA,USA.2005.184-185.
  • 9Glossner G.The sandbridge sandblaster SB3000 multithreaded CMP platform[A].5th Int Forum Appl Spec Multi-Processor SoC[C].Relais de Margaux,France.2005.18-23.
  • 10Jantsch A,Tenhunen H.Networks on chip[M].Dordrecht:Kluwer Academic Publishers,2003.

共引文献46

同被引文献24

  • 1欧阳一鸣,余雅琼,郭凯.基于同构片上网络拓扑可重构的容错硬件结构[J].计算机研究与发展,2010,47(S1):164-168. 被引量:2
  • 2张磊,李华伟,李晓维.用于片上网络的容错通信算法[J].计算机辅助设计与图形学学报,2007,19(4):508-514. 被引量:18
  • 3Dally WJ. Towles B. Route packets. not wires: on-chip interconnection networks[C] //Proceedings of Design Automation Conference. Las Vegas: Association for Computing Machinery. 2001: 684-689.
  • 4De Micheli G. Benini L. Networks on chips: technology and tools[M]. San Francisco: Morgan Kaufmann Publishers. 2006.
  • 5Topol A W. Tulipe DC La. Shi L. etal. Three-dimensional integrated circuits[J]. IBMJournal of Research and Development. 2006. 50(4/5): 491-506.
  • 6Feero B S. Pande P P. Networks-on-chip in a three?dimensional environment: a performance evaluation[J]. IEEE Transactions on Computers. 2009. 58( 1): 32-45.
  • 7Black B. Annavaram M. Brekelbaum N. et al . Die stacking (3D) microarchitecture[C] I/Proceedings of the 39th Annual IEEE/ ACM International Symposium on Microarchi -tecture. Los Alamitos: IEEE Computer Society Press. 2006: 469-479.
  • 8Zhang L. Han Y H. Xu Q. et al . On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems[J]. IEEE Transactions on Very Large Scale Integration Systems. 2009. 17(9): 1173-1186.
  • 9Fu B Z. Han Y H. MaJ. et al . An abacus turn model for time/ space -efficient reconfigurable Routing[C] //Proceedings of the 38th Annual International Symposium on Computer Architecture. New York: ACM Press. 2011: 259-270.
  • 10Feng C C. Lu Z H.Jantsch A. etal. FoN: fault-on-neighbor aware routing algorithm for networks-on-chip[C] // Proceedings of IEEE International SoC Conference. Los Alamitos: IEEE Computer Society Press. 2010: 441-446.

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