一种改进型中频数字化正交解调结构

An improved IF digital quadrature demodulation structure

提出了一种改进型中频数字化正交解调结构,通过在现场可编程门阵列内部对采样数据流拆分后,分路进行数字解调的方法,大幅降低了现场可编程门阵列的内核工作频率。解决了中频数字接收机使用超高速A/D转换器时,对可编程门阵列内核频率要求过高的问题。详细介绍了新结构的组成和工作原理,并使用SIMULINK对新结构建模和仿真,验证了其可行性。

An improved IF digital quadrature demodulation structure is proposed, which reduces the core operating frequency of the FPGA significenfly by split the sampling data flow and demodulation separately. The problem of excessively high requirement of the FPGA core-operating frequency when the high-speed A/D converter is used in an IF digital receiver is sloved. In this article, the composition and the principle of the improved structure is introduced, and the feasibility is verified by modeling and simulation in Simulink.