一种PowerPC指令集模拟器的设计与实现

A modelling and implementation method for PowerPC instruction set simulator

构建了基于PowerPC处理器的SoC软硬件协同验证平台。该平台使用层次化设计方法,支持TLM抽象层次的虚拟原型仿真,兼顾了仿真精度和速度的要求,并用软件编程的方法详细介绍了PowerPC体系指令集模拟器(ISS)的设计与实现方法。

This article describes the design of a SoC hardware/software co-verification platform, which is based on the layered approach.The platform can obtain high accuracy and simulation speed by transaction-level model （TLM） in an architecture.This project integrates instruction set simulators （ISS） as SystemC modules with TLM interfaces to the other platform components.It simulates the CPU hardware behaviour using C＋＋ program language.