基于VHDL语言的数字锁相环的设计与实现

Design and realization of DPLL based on VHDL

为了改善数字通信系统的同步性能,保证系统工作稳定、可靠,本文对锁相环电路进行了研究,利用VHDL语言进行同步单元的全数字电路设计,并利用积分电路代替微分电路减小干扰;同时为了协调锁相环相位调节速度与抗干扰能力的矛盾,设计自动调节模块,使锁相环在具有很好的抗干扰能力的前提下,做到迅速地调节相位达到锁定状态;通过MAX+plusⅡ进行仿真,给出计算机仿真结果,验证设计的正确性。

The principle of the Digital Phase Locked Loop has been discussed in order to improve the synchronization of the digital communication system and to make the system stable and reliable. A kind of DPLL bit synchronization implementation method has been designed, all based on digital circuits. And the system is designed using VHDL. In allusion to the character of signal prone to be interfered, an integral circuit is designed instead of a differential circuit. At the same time an adaptive module joins for the purpose of adjusting the controversy of PLL speed of phase adjustment and the ability of disturbance rejection. With the better ability of disturbance rejection, DPLL can adjust the phase rapidly to achieve the locked state. The VHDL program was simulated in maxplus2.The simulation results are presented and prove the validity of the design.