考虑传输线效应的时钟线网动态功耗模型

Dynamic power model of clock networks with transmission line effects

针对传递时钟信号的树型互连线网,提出了一种考虑传输线效应的动态功耗模型。在该模型中,时钟线网的每个分支互连线都采用了传输线模型,其系统输入导纳函数的计算采用了基于傅里叶级数分析的快速迭代算法。在此迭代算法基础上,根据帕斯瓦尔定理,该模型用有限阶傅里叶级数项逼近时钟线网的动态功耗。模型的精度随所取项数的增加而增加,模型的时间复杂度与项数以及时钟线网的分支数成正比。实验表明,有5项傅里叶级数逼近的模型误差小于5%,效率远高于集成电路仿真程序(SPICE)。

The size of the present VLSI （very large scale integrated） circuits scales down to deep sub micrometer, and the interconnector exhibits transmission line effects at high clock speed. However, the conventional power models did not consider these effects. Considering transmission line effects, a novel dynamic power model of clock networks is proposed. The input admittance function of clock networks, where transmission line model in all of branches, is computed iteratively based on Fourier series analysis. Based on this iterative method, dynamic power consumption of clock networks is approximated by the summation of the first Fourier-series based terms according to Parseval＇s theorem. The accuracy of the model improves with the number of terms and the computational complexity of the model is linearly proportional to the number of terms and the number of branches in clock networks. Experimental results show that the model error is less than 5% and the efficiency is significantly higher than SPICE （simulation program with integrated circuit emphasis）.