摘要
全加器是算术运算的基本单元,提高一位全加器的性能是提高运算器性能的重要途径之一。首先提出多数决定逻辑非门的概念和电路设计,然后提出一种基于多数决定逻辑非门的全加器电路设计。该全加器仅由输入电容和CMOS反向器组成,较少的管子、工作于极低电源电压、短路电流的消除是该全加器的三个主要特征。对这种新的全加器,用PSpice进行了晶体管级模拟。结果显示,这种新的全加器能正确完成加法器的逻辑功能。
A full adders is a elementary unit in arithmetic operation,so the performance improvement of the 1-bit full adder cell is a significant goa1.The concept and circuit design of low-power full adder based on majority-not gates are presented.This full-adder is mainly comprised of input capacitors and CMOS inverters.The design enjoys low power consumption,simplicity and low voltage.The new full adder was simulated with PSPICE at the transistor level.The results show that the novel structure can realize the logic function of a full adder successfully.
出处
《现代电子技术》
2010年第16期72-73,76,共3页
Modern Electronics Technique
