基于FPGA的通用FFT处理器的设计

Design of General FFT Processor Based on FPGA

介绍了一种通用的可以在低端或是高端的FPGA上实现N(N=2M,M=2,3,4…)点FFT变换的方法。设计采用基4布斯编码算法和华莱士树算法设计完成了16X16位有符号数并行乘法器,并采用此并行乘法器为核心设计了FFT算法中的基-2蝶形运算单元,设计了串并转化模块、并串转换模块、移位选择模块、溢出检测模块和地址与控制模块等其它模块,并以这些模块和FPGA内部的双口RAM和ROM为基础组成了基-2FFT算法模块。整个模块采用基-2时域抽取,顺序输入,逆序输出的方法;利用Modelsim完成了FFT模块的前后仿真;利用Matlab编写了用于比较仿真结果和Matlab中FFT函数产生的结果的程序,从而验证了仿真结果的正确性。该模块最后能够在Cyclone EP1C6Q240C8型FPGA上稳定运行在60MHz。整个FFT模块能够在183μs左右完成1024点的16位定点复数FFT运算,能够满足一般工程的要求。该方法也可以用于实现更低点数或是更高点数的FFT运算。

Introduces a general method which can be realized in the low-end or high-end FPGA to achieve N（N=2M,M=2,3,4 …） point FFT. The 16X16-bits signed number parallel multiplier is completed with radix-4 Booth encoding algorithm and Wallace tree algorithm in the design.The parallel multiplier is used to design the radix-2 butterfly unit of the core design of the FFT algorithm,and the parallel-serial conversion module,serial-parallel conversion module,shift select module,overflow detection module,address and control module and other modules are designed.The radix-2 FFT module is formd based on these modules and the internal dual-port RAM and ROM of FPGA.The whole module uses the way of time-domain-based extraction,the order of input,output reverse.The pre-simulation and the post-simulation of the design is done by Modelsim.The code used to differ the simulation result from the FFT function in Matlab is created in Matlab and the simulation result is proved to be correct.Finally the design can be able to run at 60MHz in the Cyclone EP1C6Q240C8 stably.The FFT module can realize 1024 points,16-bit fixed-point complex FFT at about 183μs,and it can meet the general engineering requirements.This method can also be used to achieve a lower point or higher points FFT.