12位50 MHz流水线ADC采样保持电路实现

Implementation of Sample and Hold Circuit for 12-Bit 50 MHz Pipelined ADC

对采样保持电路进行研究,对增益提高的运算放大器进行2阶系统模拟,得到最佳设计参数;提出一种栅压自举开关电路结构;设计了一个用于12位50 MHz流水线A/D转换器的采样保持电路。采用SMIC 0.35 μm混合CMOS工艺,对整个A/D转换器进行实现。测试结果表明,采样保持电路完全满足设计要求。

Sample and hold circuit was studied,and a second-order system simulation was made on gain-boots operational amplifier to obtain optimal parameters.A novel structure of bootstrap switch was presented,and a sample and hold circuit for 12-bit 50 MHz pipelined A/D converter was designed and implemented in SMIC＇s 0.35 μm mixed-signal CMOS process.Test results showed that the proposed sample and hold circuit fulfilled the requirements of 12-bit 50 MHz pipelined A/D converter.