集成宽频Σ-Δ分数频率合成器的实现

Implementation of Integrated Wideband Σ-Δ Fractional-N Frequency Synthesizer

提出了一种新型低噪声、宽跟踪范围的集成分数频率合成器。该合成器采用3位3阶Σ-Δ调制器和对数字信号进行粗调、对模拟信号进行微调的宽频开关电容阵列LC压控振荡器,其中,数字和模拟调谐控制信号由4位2级并行流水线A/D转换器产生。详细分析了该合成器的结构和实现电路,并采用0.25 μm CMOS工艺实现。测试结果显示,电路在偏离载波频率10 kHz处带内相位噪声为-86.2 dBc/Hz,在偏离载波频率2 MHz处的带外相位噪声为-130 dBc/Hz,且具有小于5 Hz的频谱分辨率。

A novel low noise and wideband fractional-N frequency synthesizer was presented,in which a 3-bit third-order sigma-delta modulator and a controllable switched capacitor LC VCO were used.The control signals were generated by a 4-bit two-stage pipelined ADC.The synthesizer was fabricated in 0.25 μm CMOS process.Test results showed that the circuit had an in-band and an out-of-band phase noise of about-86.2 dBc/Hz and-130 dBc/Hz at 10 kHz and 2 MHz offset frequencies,respectively,and the frequency resolution for the synthesizer was less than 5 Hz.