摘要
采用一种加速全定制IC设计的方法,完成了基于CSMC(华润上华)0.5 μm工艺的32位加法器的设计。使用动态差分多米诺逻辑,实现了基于Brent-Kung树结构的超前进位加法器;采用Mentor Graphics Advance MS仿真软件,加速进行Spice网表的仿真和版图后仿。仿真结果验证了Spice网表的正确性,得出加法器在版图后仿的关键路径延时为4.62 ns,整个设计流程可以应用于其他一些重要核心单元的全定制设计。
A 32-bit adder based on CSMC＇s 0.5 μm process was designed by using an accelerated design method for full-custom IC.Look-ahead adder based on Brent-Kung tree structure was realized by using dynamic difference domino logic,and Advance MS software of Mentor Graphics was used to accelerate simulation of Spice netlist and post-layout simulation.Results showed that the crucial path delay in post simulation was 4.62 ns.The design flow is applicable for full-custom design of some other core cells.
出处
《微电子学》
CAS
CSCD
北大核心
2010年第4期566-569,共4页
Microelectronics
