期刊文献+

面向扩频通信的可重构阵列电路研究

Study on Spread Spectrum Communication Oriented Reconfigurable Array Circuit
下载PDF
导出
摘要 传统的可重构电路主要由细粒度数据处理单元组成,但是其实现的运算功能单一,且布线复杂,限制了可重构SoC电路的通用性和灵活性。针对以上问题,根据通信领域基带信号处理的运算特点,设计了一种新型可重构阵列电路,可作为运算模块嵌入可重构SoC,此阵列由粗粒度数据处理单元构成的细胞互联组成。针对基带信号数据位宽多样的特点,细胞可重构实现多种算子。通过在阵列中每个细胞内部都嵌入独立配置存储器,采用并行数据配置电路的方式,以降低阵列的重构时间开销,实现整个阵列的快速重构。以伪码捕获为例,对设计的电路进行仿真。结果显示,设计的结构布线方法简单、通用性及灵活性强。 Conventional reconfigurable circuit consisted of fine-grained units has disadvantages such as few computing functions and complicated wiring,which limits its application to reconfigurable SOC.To solve these problems,a new reconfigurable array circuit was designed based on the operational features of communication base-band signal processing,which could be embedded into reconfigurable SOC as computing module.This array circuit was composed of cells consisting of coarse-grained units,which could be reconstructed to achieve a variety of operators based on various data widths of base-band data signal.In the array circuit,separate configuration memory was embedded into each cell,and data parallel configuration was used to reduce reconstruction time.Finally,with pseudo-code acquisition as an example,the proposed circuit was simulated to demonstrate the simplicity,universality and flexibility.
出处 《微电子学》 CAS CSCD 北大核心 2010年第4期570-574,共5页 Microelectronics
基金 国家自然科学基金资助项目(60871009 60501022) 航空科学基金资助项目(2009ZD52045)
关键词 数字扩频通信 信号处理 可重构阵列电路 Digital spread spectrum communication Signal processing Reconfigurable array circuit
  • 相关文献

参考文献11

  • 1刘洋,尹蕾,李广军.基于流水线技术的可重构体系结构的研究与设计[J].微电子学,2008,38(4):593-595. 被引量:2
  • 2陈黎明,邹雪城,雷鑑铭,刘政林.动态可重构高速缓存结构的研究与设计[J].微电子学,2007,37(6):895-898. 被引量:2
  • 3徐新民,王倩,严晓浪.FPGA布线通道分布对面积效率的影响研究[J].电子与信息学报,2006,28(10):1959-1962. 被引量:2
  • 4LANUZZA M,PERRI S,CORSONELLO P,et al.A new reconfigurable coarse-grain architecture for multimedia applications[C] // Proc NASA/ESA Conf Adap Hardware Syst.Edinburgh,UK.2007:119-126.
  • 5HARTENSTEIN R.Coarse grain reconfigurable architectures[C] // Proc ASP-DAC Conf Design Autom.New York,USA.2001:564-569.
  • 6MYJAK M J.A medium-grain reconfigurable architecture for digital signal processing[D].Washington D C:Washington State University.2006.
  • 7FERREIRA R,DAMIANY R,VENDRAMINI J,et al.On simplifying placement and routing by extending coarse-grained reconfigurable arrays with omega networks[C] // 5th Int Workshop Appl Reconf Comp.2009,49(5):145-156.
  • 8WANG B,KWON H M.PN code acquisition using smart antenna for spread-spectrum wireless communications[J].Vehicular Technology,2003,52(1):142-149.
  • 9SHARMA A,HAUCK S,EBELING C.Architecture adaptive routability-driven placement for FPGAs[C] // Proc Int Conf Field Program Logic Applica.Tampere,Finland.2005:427-432.
  • 10LI C-M,LI H-J.A novel RAKE receiver finger number decision rule[J].Antennas and Wireless Propagation Letters,2003,2(1):277-280.

二级参考文献35

  • 1覃祥菊,朱明程,张太镒,魏忠义.FPGA动态可重构技术原理及实现方法分析[J].电子器件,2004,27(2):277-282. 被引量:44
  • 2Milagros Fernández,Nader Bagherzadeh,Rafael Maestre,Roman Hermida,Fadi Kurdahi,Marcos Sanchez-Elez.A data scheduler for multi-context reconfigurable architectures[C].Proceedings of the 14th international symposium on Systems synthesis,Montreal,P.Q.,Canada,September 2001,177-182.
  • 3Maestre R,Fernandez M,Hermida R,Bagherzadeh N.A framework for scheduling and context allocation in reconfigurable computing[C].12th International Symposium on System Synthesis,Boca Raton,Florida,November 1999.
  • 4Chengzhi Pan,Nader Bagherzadeh,Amir Hosein Kamalizad,Arezou Koohi.Design and analysis of a programmable single-chip architecture for DVB-T base-band receiver[C].Design,Automation and Test in Europe.Conference and Exhibition (DATE'03),Munich,Germany,2003:468-472.
  • 5Intel.IntelrPentiumr 4 and Intelr XeonTM processor optimization reference manual[EB/OL].http://www.intel.com/cd/ids/ developer/asmo-na/eng/microprocessors/ia32/pentium4/index.htm 2004.
  • 6Chen W H,Smith C H,Fralick S C.A fast computational algorithm for the discrete cosine transform[J].IEEE Transaction on Communications,1977,25(9):1004-1009.
  • 7Singh H,Lee M H,Lu G,Kurdahi F J,Bagherzadeh N,Filho E M C.MorphoSys:an integrated reconfigurable system for data-parallel and computation -intensive applications[J].IEEE Transaction on Computers,2000,49(5):465-481.
  • 8Lu G,Singh H,Lee M,et al.The morphoSys dynamically reconfigurable system-on-chip[C].In:The First NASA/DOD Workshop on Evolvable Hardware,Pasadena,California,1999,152-161.
  • 9Singh H,Ming-Hau Lee,Guangming Lu,Kurdahi F J,Bagherzadeh N,Lang T,Heaton R,Filho E M C.MorphoSys:an Integrated Re-Configurable Architecture.The application of information technologies (Computer Science) to mission systems[M].Monterey,CA,USA,April 1998.
  • 10Lu Guang-ming,Ming-Hau Lee,Nader Bagherzadeh,Rafael Maestre,Eliseu Filho,Fadi Kurdahi,Hartej Singh MorphoSys:case study of a reconfigurable computing system targeting multimedia applications[C].37th Conference on Design Automation (DAC'00) June 2000,Los Angeles,CA,573-578.

共引文献9

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部