一种位复用近似LRU替换算法的分析与研究

Study of Bit Reuse Pseudo LRU Replacement Algorithm

提出并实现了4-way组相联高速缓存设计[1]中能够减少电路复杂性、节省Valid RAM空间的5-bit位复用近似LRU算法,其基本方法是通过位比较对4-way数据访问先后进行排序、对Valid位和比较位进行复用。给出了不命中时的替换选择电路逻辑和通过VHDL实现后的测试结果。相关结果表明,该算法实现电路简单,占用面积小,且命中率高:在指令高速缓存设计中,高速缓存大小为1 kB时,测试的平均命中率为90.2%,4 kB时为92.3%,16 kB时为94.2%。

A 5-bit reuse pseudo LRU algorithm was proposed and implemented to reduce circuit complexity and save valid RAM space in 4-way set-associative cache design[1],in which data access was sorted by bit comparison,and valid-bit and comparison-bit were reused.Replacement logic circuit on cache miss and test results of VHDL implementation were presented.It has been shown that the algorithm was easy to be implemented,the circuit only occupied a small chip area and it had a high cache hit rate.In instruction cache design,the average hit rate was 90.2%,92.3% and 94.2% for 1 kB,4 kB and 16 kB cache size,respectively.