基于FPGA的二-十进制转码器设计

Binary to decimal converter design based on FPGA

针对二进制转十进制(BCD)转码器的FPGA实现目标,提出了一种高效、易于重构的转码器设计方案。并在FPGA开发板上成功地实现了该设计,验证结果表明,与使用中规模集成电路IP核(SN74185A)实现的7 bit、10 bit和12 bit的转码器相比,本设计可以分别节约28.5%、47.6%和49.6%的硬件实现代价(逻辑单元LEs);同时,电路的路径延迟也分别减少了0.7 ns、2.1 ns和8.9 ns.

In order to implement binary to decimal converter on a field programmable gate array（FPGA） chip, an efficient and reconfigurable design is proposed. Moreover, the design has been successfully implemented on FPGA development board. Experimen- tal results show that compared with the 7 bit, 10 bit and 12 bit binary to BCD converters implemented with medium scale integra- tion（MSI） SN74185A intellectual property （IP） cores, the design can achieve about 28.5%, 47.6% and 49.6% implemented cost saving of the logic elements（LEs） respectively. Meanwhile, time propagation delay（TPD） can decrease by 0.7 ns, 2.1 ns and 8.9 ns respectively.