高性能EBCOT编码加速算法及其实现结构

High performance EBCOT algorithm and VLSI architecture

提出了具有零系数检测并行处理的EBCOT编码算法及硬件实现结构.通过分析JPEG2000中小波变换系数的精度分布,指出在变换系数中存在3种不同的零系数模式——零列、零条带和零码块,并且在EBCOT编码结构中,可以同时获得每一个位平面及对应编码过程的编码信息,所以位平面与编码过程可以全并行处理.基于以上分析,给出了高速处理EBCOT软件算法和VLSI结构.理论分析和软硬件实验结果表明,具有零系数检测机制的位平面与编码过程全并行处理所需的时钟周期最少,综合最高时钟频率可达79.466MHz,对于1 024×1 024的灰度图像处理速度可达79帧/秒.

We propose an efficient coding algorithm and architecture composed of the bit plane-parallel and pass-parallel coder with efficient zero coefficients detection for EBCOT entropy encoder used in JPEG2000.After the detailed analysis of wavelet coefficients＇ precision and distribution in JPEG2000,there are three main modes of zero coefficients in the wavelet domain,i.e.,zero column,zero stripe and zero code block.And we also discover that the coding information on each bit plane and the corresponding passes can be obtained simultaneously in the hardware structure.Therefore,bit plane-parallel and pass-parallel coding with zero detection（BPPP-ZD） is proposed,and its VLSI architecture is shown in detail.Analysis and the corresponding software/hardware experimental results show that the proposed architecture reduces the processing time greatly compared with other architechures,and a prototype chip is synthesized which can process 1024×1024 gray level images with 79 frames per second at the working frequency of 79.466MHz.