多码率RS码部分并行译码结构设计

Partially parallel decoder structure of multi-rate RS codes

为了满足在一个通信系统中使用多码率RS(Reed-Solomon)码的需求,提出了一种多码率部分并行结构的RS码译码器.按照功能,该译码器可分为伴随式计算模块,关键方程求解模块以及错误位置和错误值求解模块3个主要组成部分.针对符合CCSDS标准的2种RS码的特点,将运算系数相同的伴随式计算子单元进行复用;在关键方程的求解运算中使用一种新颖的部分并行结构,使得复用部分和非复用部分的运算周期相同,以减少运算等待时间,提高译码效率;在错误位置和错误值求解中采用查表方式完成Forney算法的系数相乘,并复用求逆查表运算和系数相同的钱氏搜索计算子单元,以减少资源的消耗.通过码率选择信号,可以选择RS(255,223)和RS(255,239)2种译码模式.通过Altera公司的FPGA(Field Pro-grammable Gate Array)对该多码率译码器进行了硬件实现,结果显示此译码器仅消耗2981个逻辑单元和9472 bit的存储器资源,大大低于2种单一码率译码器消耗资源的总和.

To meet the requirement of using multi-rate RS（Reed-Solomon） codes in the communication system,a multi-rate partially parallel RS codes decoder architecture was presented.This decoder can be divided into three major blocks by its function： the syndrome computation block,the key-equation solver block and the Chien search and error evaluator block.According to the characteristic of the two RS codes specified in CCSDS standards,the syndrome computation cells of different code rates which have the same factor share the same hardware resources.A novel partial parallel architecture was used in solving the key-equation,which makes multiplexed units and non-multiplexed units operate concurrently,so as to reduce the waiting time in computation as well as improve decoding efficiency.In Chien search and error evaluator block,look-up tables were used to realize the multiply operation in Forney algorithm.Besides,multiplexed structures were used in inverse operation cells and Chien search cells in order to reduce the hardware resources.Using pin selection,two decoding modes,namely,RS（255,223） and RS（255,239） were supported.The synthesis result which is implemented in Altera＇s FPGA devices indicates that the proposed multi-rate RS code decoder using 2 981 logic elements and 9 472 memory bits.