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Multilevel Optimization for Large-Scale Hierarchical FPGA Placement

Multilevel Optimization for Large-Scale Hierarchical FPGA Placement
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摘要 This paper proposes a multilevel placer targeted at hierarchical FPGA（Field Programmable Gate Array） devices.The placer is based on multilevel optimization method which combines the multilevel bottom-up clustering process and top-down placement process into a V-cycle.It provides superior wirelength results over a known heuristic high-quality placement tool on a set of large circuits,when restricted to a short run time.For example,it can generate a placement result for a circuit with 5000 4-LUTs（4-Input Look Up Tables） in 70 seconds,almost 30%decrease of wirelength compared with than the heuristic implementation that takes over 500 seconds.We have verified our algorithm yields good quality-time tradeoff results as a low-temperature simulated annealing refinement process can only improve the result by an average of 1.11%at the cost of over 25-fold runtime. This paper proposes a multilevel placer targeted at hierarchical FPGA（Field Programmable Gate Array） devices.The placer is based on multilevel optimization method which combines the multilevel bottom-up clustering process and top-down placement process into a V-cycle.It provides superior wirelength results over a known heuristic high-quality placement tool on a set of large circuits,when restricted to a short run time.For example,it can generate a placement result for a circuit with 5000 4-LUTs（4-Input Look Up Tables） in 70 seconds,almost 30%decrease of wirelength compared with than the heuristic implementation that takes over 500 seconds.We have verified our algorithm yields good quality-time tradeoff results as a low-temperature simulated annealing refinement process can only improve the result by an average of 1.11%at the cost of over 25-fold runtime.
作者 戴晖 周强 边计年
机构地区 EDA Lab
出处 《Journal of Computer Science & Technology》 SCIE EI CSCD 2010年第5期1083-1091,共9页 计算机科学技术学报（英文版）
基金 supported by the National Natural Science Foundation of China under Grant Nos.60876026 and 60833004.
关键词 multilevel optimization LARGE-SCALE hierarchical FPGA PLACEMENT multilevel optimization large-scale hierarchical FPGA placement
分类号 TN791 [电子电信—电路与系统] TU311.3 [建筑科学—结构工程]
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Journal of Computer Science & Technology
2010年 第5期

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