使用支持向量机的微处理器验证向量优化方法

An approach to microprocessor simulation vector optimization using SVM

为了解决微处理器仿真验证中随机验证向量质量不高的问题,提出了一种基于支持向量机(SVM)的验证向量优化方法。该方法将已仿真运行的验证向量及其覆盖率信息作为支持向量机的样本进行有监督学习,得到验证向量关于功能覆盖点的分类器。利用训练后的分类器对于新产生的验证向量进行预测,并丢弃预测中不能提高覆盖率的冗余验证向量。实验数据表明该方法能准确地过滤冗余验证向量,提高仿真运行的验证向量的质量。和完全随机的验证向量生成方法相比,该方法达到相同的功能覆盖率仅需要前者1/3的验证向量。

This paper proposes a simulation vector filter method based on support vector machines （SVM） and functional coverage to cope with the problem that most random simulation vectors are redundant in simulation-based microprocessor verifi- cation. A SVM is used to learn the trained simulation vectors and their coverage information, and the new generated sim- ulation vectors are filtered by the learned result. Those which can not improve the functional coverage are redundant and should be discarded. The experimental results based on application of the proposed methodology demonstrate that this technique can precisely filter the redundant simulation vectors to improve the efficiency of verification. Compared with the totally random method, only one third of the simulation vectors are needed to be simulated to reach the same functional coverage.