期刊文献+

OFDM系统中FFT处理器的版图设计 被引量:1

Layout design of FFT processor for OFDM system
原文传递
导出
摘要 用Astro工具设计FFT处理器版图流程.在设计FFT处理器版图过程中,采用新的电源网络设计方法进行电源/地Pad数量、电源环和电源条设计,采用布线前设定高层跳线方式和布线后插入保护二极管方式消除天线效应,通过整个版图设计过程防止串扰效应实现串扰不超过设定的阈值,并对布局阻塞违规和布线违规提出解决办法.实现了满足时序和制造工艺要求的FFT处理器版图,达到项目设定的各项性能指标要求. Introduces layout design flow of FFT processor based on Astro. In the FFT processor layout design, from researching the new method of power network design to designing the power/ground pad number, power ring and power strap. By setting to jump the wire with a higher - layer metal before routing and inserting diode after routing, the antenna effect is chminated. The crosstalk is considered at each stage of the whole layout design, which must be controled in the threshold. The issue about Place block and routing violations is solved. The FFT processor layout meets the demand timing and technology and the whole system reaches the target.
出处 《福州大学学报(自然科学版)》 CAS CSCD 北大核心 2010年第4期538-543,共6页 Journal of Fuzhou University(Natural Science Edition)
基金 福建省自然科学基金资助项目(2007J0003) 福建省教育厅科研资助项目(JA09001)
关键词 OFDM系统 FFT处理器 版图设计 电源网络设计 OFDM system FFT processor layout design power network design
  • 相关文献

参考文献10

  • 1万红星,陈禾,韩月秋.实时可重配置FFT处理器的ASIC设计[J].北京理工大学学报,2006,26(4):342-344. 被引量:5
  • 2Lin Y W, Lee C Y . Design of an FFT/IFFT Processor for MIMO OFDM Systems[J]. IEEE Transactions on Circuits and Sys tem, 2007, CAS -54(4) : 807 -815.
  • 3肖昊,向波,陈赟,曾晓洋.高效可配置FFT处理器的VLSI设计及其应用[J].计算机辅助设计与图形学学报,2009,21(2):209-213. 被引量:5
  • 4Lee J, Lee H, Cho S, etal. A high - speed, low complexity radix - 24 FFT processor for MB - OFDM UWB system [ C ]// IEEE Int Symp Circuits and Systems, 2006:4 719 -4 722.
  • 5Kiran G, Chien - In Chen H. Configurable and expandable FFT processor for wideband communications [ C ]// Proceedings of IEEE International Instrumentation and Measurement Technology Conference, 2007:1 -5.
  • 6樊俊峰,王国雄,沈海斌,楼久怀.深亚微米下芯片电源网络的设计和验证[J].电子器件,2006,29(4):1164-1167. 被引量:1
  • 7Wang M G, Yang X J, Sarrafzadeh M. Congesion minimization during placement [ J ]. IEEE Transactions on Computer - aided Design of Integrated Circuits and Systems, 2000, 19(10) : 1 140 -1 148.
  • 8千路,林平分.ASIC后端设计中的时钟偏移以及时钟树综合[J].半导体技术,2008,33(6):527-529. 被引量:15
  • 9Becer M, Vaidyanathan R, Chanhee O, et al. Crosstalk noise control in a SOC physical design flow[ J ]. IEEE Transaction on Computer- Aided Design of Integrated Circuits and Systems, 2004, 23 (4) : 37 -42.
  • 10Rabaey J M, Chandrakasan A, Nikolic B. Digital integrated circuits: a design PersPective [ M ]. 2nd ed.北京:电子工业出版社,2008:156-339.

二级参考文献31

  • 1高振斌,陈禾,韩月秋.可变2^n点流水线FFT处理器的设计与实现[J].北京理工大学学报,2005,25(3):268-271. 被引量:4
  • 2万红星,陈禾,韩月秋.一种高速并行FFT处理器的VLSI结构设计[J].电子技术应用,2005,31(5):45-48. 被引量:15
  • 3邓博仁,王金城,金西.基于深亚微米下时钟树算法优化的研究[J].半导体技术,2005,30(10):42-45. 被引量:2
  • 4Lin Y W, IJu H Y, Lee C Y. A 1- GS/s FFT/IFFT processor for UWB applications [J]. IEEE Journal of Solid State Circuits, 2005, 40(8): 1726-1735.
  • 5Maharatna K, Grass E, Jagdhold U. A 64 point Fourier transform chip for high-speed wireless LAN application using OFI)M[J]. IEEE Journal of SoLid-State Circuits, 2004, 39 (3):484-493.
  • 6Sansaloni T, Perez Pascual A, Torres V, et al. Efficient pipeline FFT processors for WLAN MIMO OFDM systems [J]. IET Journal of Electronics Letters, 2005, 41 (19) : 1043- 1044.
  • 7Lin Y W, Liu H Y, Lee C Y. A dynamic scaling FFT processor for DVB-T applications [J]. IEEE Journal of Solid State Circuits, 2004, 39(11): 2005-2013.
  • 8LiXJ, LaiZ S, CuiJ M. Alow power and small areaFFT processor for OFDM demodulator [J]. IEEE Transactions on Consumer Electronics, 2007, 53(2): 274-277.
  • 9Jia L H, Gao Y H, Tenhunen H. A pipelined shared memory architecture for FFT processors[C] // Proceedings of the 42nd Midwest Symposium on Circuits and Systems, Las Cruces, 1999, 2:804-807.
  • 10Cooley J W, Tukey J W. An algorithm for the machine calculation of complex Fourier series[J]. Mathematics of Computation, 1965, 19(90):297-301.

共引文献22

同被引文献6

  • 1时昕,王东辉,侯朝焕.深亚微米SoC中的电源/地网络设计[J].微电子学与计算机,2004,21(12):198-202. 被引量:10
  • 2王丽英,杨军,罗岚.深亚微米SOC芯片物理设计中基于串扰的时序收敛方法[J].微电子学与计算机,2006,23(1):85-88. 被引量:2
  • 3唐彬,徐强,王莉薇.数字IC设计-方法、技巧与实践[M].北京:机械工业出版社,2006.
  • 4Brunvand E. Digital VLSI chip design with.cadence and synopsys CAD tools [ M ]. Boston: Addison - Wesley Publishing Company, 2009.
  • 5Becer M, Vaidyanathan R, Oh C, et al. Crosstalk noise control in an SOC physical design flow[ J ]. IEEE Transaction on Com- puter - Aided Design of Integrated Circuits and Systems, 2004, 23 (4) : 488 - 497.
  • 6Zhang Lizheng, Chen Weijen, Hu Yuhen, et al. Statistical static timing analysis with conditional linear btAX/MIN approximation and extended canonical timing model [ J ]. IEEE Transaction on Computer - Aided Design of Integrated Circuits and Systems, 2006, 25(6) : 1 183 -1 191.

引证文献1

二级引证文献6

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部