高速电路中的信号完整性及仿真

Signal integrality and simulation in high speed circuit

为在高速数字系统设计中,随着数字电路工作频率的提高,信号完整性问题变得无处不在,对电路稳定性影响巨大。针对高速PCB设计要求讨论了设计中涉及的延迟、反射、串扰等信号完整性问题,分析了各种破坏信号完整性的原因,并提供了改善信号完整性的对策。通过采用Cadence/SpecctraQuest仿真工具对一ARM9核心板电路板中的高速SDRAM时钟信号线的布局布线后的仿真,给处了由于没有阻抗不匹配造成设计失败的实例,重点分析了高速电路板中存在的阻抗匹配问题,并给出了利用Cadence/SpecctraQuest解决信号完整性问题办法。

In the high-speed digital system design,with the increase in frequency of digital circuits,signal integrity issues become ubiquitous,a tremendous impact on the circuit stability.Discussion of the design requirements for high-speed PCB design involved in the Propagation Delay,Reflection,Crosstalk and other signal integrity problems,Whit the help of Cadence/SpecctraQuest for an ARM9 core board high-speed circuit board layout of signal lines of the SDRAM after the routed,analysis the signal integrity issues in high-speed circuit board,and gives the solutions.