基于FPGA的基8-FFT处理器设计

Radix-8 FFT Processor Design Based on FPGA

提出了在现场可编程门阵列（FPGA）上实现4096点基8快速傅里叶变换（FFT）算法的设计方案。方案对蝶形器、旋转因子产生器和输入/输出接口进行了分析和优化,整个算法的流程采用了流水线的工作方式,提高了运算速度并减小了FPGA内部资源的占用。通过仿真测试,并同Matlab定点模型进行了对比。本设计方案在100MHz的时钟下,完成4096点基8-FFT运算需要2.048μs,完全满足高速数字信号处理的要求。

A design of 4096-point radix-8 FFT is implemented on Field-Programming Gate Array （FPGA）. Traditional radix-2 and radix-4 FFT processors could not satisfy the requirements of modern high-speed digital signal processing, so the radix-8 shared-memory architecture is used at the top-level. The butterfly module, the twiddle factor generation module, the input-output interface module are analyzed and optimized. A novel method to generate twiddle factors is proposed and compared with the traditional method. The pipeline style design increases the computing speed and decreases the FPGA resource utilization. Simulation verification is done and the result is compared with that of Matlab fixed-point model. The design is finally programmed to an Altera EP2S60F672I4 device and is verified with the help of a digital signal processor. The computing results with various input patterns are retrieved to Matlab and compared with the fixed-point model bit by bit. Under the clock frequency of 100MHz, the design takes 2.048μs to finish 4096-point radix-8 FFT, so it can meet the requirement of high speed digital signal processing.