数字电路多故障测试生成的神经网络方法研究

A Multiple Faults Test Generation Method for Digital Circuits with Artificial Neural Network

本文深入研究基于Ｈｏｐｆｉｅｌｄ神经网络的数字电路多故障测试生成方法，该方法利用电路基本逻辑门和Ｈｏｐｆｉｅｌｄ网络的特性，建立多故障测试生成的神经网络模型，通过求解网络能量函数的最小值点获得给定多故障的测试矢量。文中提出了加速测试生成的技术策略，为多故障的测试提供了一种可能的新途径。

A multiple faults test generation method for digital circuits is studied first. The method develops basic gate circuits and neural networks to establish the test model, and generates the test patterns for multiple faults by means of computing the global minima of the energy function of the neural network which accords with the circuit under test. We next focus on the designs and implements of the method, a lot of strategies are proposed in order to accelerate the multiple faults test generation process, such as the reduction of the size of neural network. The simulation results are also given, which indicate that the algorithms using the above strategies are effective.