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一种双游程编码的测试数据压缩方案 被引量：3

Scheme of Test Data Compression Based on Dual-run-length Code
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摘要 SOC芯片测试中一个主要的挑战就是处理大量的测试数据.为了减少芯片测试中的测试数据,提出了一种双游程的编码方案,采用变长到变长的编码方式对0游程和1游程进行编码.该算法在编码时同时考虑0游程和1游程,大大减少了测试数据中短游程的数量,同时文中给出了一种基于有限状态机的解压缩算法的实现方案.理论分析和实验结果证明该方案具有高压缩率、硬件实现简单等特点. One of the major challenges in testing a system-on-a-chip is dealing with a large volume of test data.To reduce the volume of test data,dual-run-length code is proposed in this paper,a variable-to-variable run-length code based on encoding both runs of 0s and 1s.Both runs of 0s and 1s are considered in this method so as to reduce the number of short runs,and the circuit structure of decoder with FSM is proposed.Theoretical analysis and experimental results show that this schemes is a very efficient compression method.
作者 商进 张礼勇
机构地区 哈尔滨理工大学测控技术与通信工程学院 黑龙江工程学院电子工程系
出处 《哈尔滨理工大学学报》 CAS 北大核心 2010年第4期19-22,共4页 Journal of Harbin University of Science and Technology
基金 黑龙江省教育厅科学技术研究项目(10551Z0007)
关键词 测试数据压缩 解压 双游程编码 test data compression decompression dual-run-length code
分类号 TP391.76 [自动化与计算机技术—计算机应用技术]
  • 相关文献

参考文献12

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二级参考文献11

  • 1韩银和,李晓维,徐勇军,李华伟.应用Variable-Tail编码压缩的测试资源划分方法[J].电子学报,2004,32(8):1346-1350. 被引量：27
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共引文献32

同被引文献20

  • 1冯志全,范平,张少白,王玉茹,成谢锋.一种无失真图像数据压缩算法[J].计算机应用,2001,21(z1):134-134. 被引量：3
  • 2刘於勋 ,李国伟 ,马丽 .浅谈栅格数据结构及其压缩编码方法[J].河南工业大学学报（社会科学版）,2004(3):5-6. 被引量：3
  • 3韩银和,李晓维.测试数据压缩和测试功耗协同优化技术[J].计算机辅助设计与图形学学报,2005,17(6):1307-1311. 被引量：15
  • 4乌伦,刘瑜,张晶,等.地理信息系统-原理、方法和应用[M].北京:科学出版社,2001.
  • 5Gregory A Plumb.Compression of Continuous Spatial Data in the Raster Digital Format[J].Computers&Geosciences,1993,19(4):493-497.
  • 6David A.Huffman.A Method for the Construction of Minimum-Redundancy Codes[J].Proceedings of the IRE,1952(9):1098-1101.
  • 7Chandra A,Chakrabarty K. System-on-a-chip test-data compression and decompression architectures based on- Golomb codes[J]. IEEE Transactions on Computer-Ai- ded Design of Integrated Circuits and Systems, 2001, 20(3) : 355-368.
  • 8Nourani M, Tehranipour M. RL-huffman encoding for test compression and power reduction in scan applica- tion[J]. ACM Trans Des Autom Electron Syst, 2005, 10(1) : 91-115.
  • 9Chandra A,Chakrabarty K. Test data compression and test resource partitioningforsystem-on-a-chip using fre- quency-directedrun-length ( FDR ) coeds [ J ]. IEEETransactionson Computer Aided Design of Inte-grated CircuitsandSystems, 2003,52 (8) : 1076-1088.
  • 10王钢,高宏亮.基于FPGA交织编码的设计与实现[J].哈尔滨理工大学学报,2009,14(1):63-66. 被引量：11

引证文献3

二级引证文献1

哈尔滨理工大学学报
2010年 第4期

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