一种具有欠采样功能的采样保持电路

Sample-Hold Amplifier Utilizing Under-Sampling Technique

设计并实现了低功耗的欠采样保持(under-sampling and hold)电路,该电路可应用在模数转换器的前端.该电路选取全差分的电荷传递式开关电容结构,具有欠采样功能的高速自举开关及连续时间共模负反馈结构的两级运算放大器.该电路基于SMIC CMOS 0.18μm 1P6M工艺绘制,测试结果表明,在电源电压为3.3 V,采样频率fs为2 MHz,信号频率fa为2.01 MHz时,总功耗约为1 mW,等效信号频率fa'为10 kHz的信噪失真比RSND为47 dB.该电路可以广泛应用于频移键控调制系统中.

This article describes the design and performance of low power under-sampling and hold amplifier used in high speed analog-to-digital converter.The designed circuitry consists of full differential switched capacitor circuit,high speed bootstrapped switch with under-sampling function and two-stage amplifier with continuous common voltage feed-back.The layout of the circuits is plotted under SMIC CMOS 0.18 μm 1P6M process with 3.3 V supply.The performance of system shows that the SNDR can reach 47 dB when the sampling frequency is 2 MHz with the power of 1 mW and the signal frequency is 2.01 MHz（equivalent to 10 kHz）.The circuit can be widely applied in the FSK system.