分块归零处理Turbo译码器设计与实现

Design and implementation of Turbo decoder based on frame splitting and trellis zero termination

分块归零Turbo编码方案通过采用与分块并行译码相适应的帧分裂和归零编码处理,使码字具有适应分块并行译码的结构特性。相应算法仿真和FPGA设计实现表明,该方案首先无需在相邻分块间考虑重叠比特以保证误码性能,有助于提高短码块长时的译码吞吐率;其次,分块归零处理也使得译码单元内部的状态度量初始值为一个确定值,从而使得各个SISO之间的译码更加独立,降低了译码器FPGA实现复杂度;此外,分块归零的编码结构特性在迭代译码时能够更快收敛。

Turbo encoding with frame splitting and trellis zero termination provides a suitable structure for implementing the segmented-based parallel Turbo decoding.The performance simulation, together with the FPGA design and implementation of the proposed Turbo coding scheme unveils that,the overlapping between neighboring segments to guarantee the achieved reliability can be saved, which may be helpful to achieve higher decoding throughput especially for short block size cases.Secondly, the frame splitting with trellis zero termination encoding process implies that both the initial and the end states of each segment are specified with the known all-zeros state, and this may make the SISO decoder respecting to each sub-block independent from each other,which may give rise to a simplified FPGA design.Finally,the segment based trellis zero termination structure property is favorable for a faster convergence in iterative decoding.