摘要
随着采样频率和A/D变换器位数的增加,时钟抖动和相位噪声对数据采集系统性能的影响更加显著。从相位噪声的双边带功率谱密度出发,详细分析了相位噪声和周期间抖动之间的联系,指出了相位噪声的不同频段对周期间抖动的影响,讨论了数据采集信噪比与时钟抖动和相位噪声之间的关系;并通过仿真给予定量的计算,对时钟源和数据采集系统的设计提供了一些建议;最后,利用某雷达数据采集系统进行实验,给出了相关实验结果。
The effect of clock jitter and phase noise on data acquisition system performance is more profound as the increase of sampling frequency and the bit of A/D converter.The relationship between phase noise and time jitter is discussed,and the characteristics of jitter performance of phase noise at different frequency offsets is revealed;then the effect of clock jitter on the signal-to-noise ratio of A/D converter is analyzed.Additionally,the quantitative result is obtained though simulation,and suggestion is presented for the designers of clock source and data acquisition system.Finally,the experimental result is also presented.
出处
《雷达科学与技术》
2010年第4期372-375,共4页
Radar Science and Technology
关键词
时钟抖动
相位噪声
A/D变换器
信噪比
采样时钟
clock jitter
phase noise
A/D converter
signal-to-noise ratio
sampling clock
