CMOS集成电路设计中的功耗优化技术

Power optimization techniques in CMOS IC design

对近年来发展起来的ＣＭＯＳ（互补型金属－氧化物－半导体）集成电路的各种低功耗设计方法进行了分析和比较。阐述了在电路级、逻辑级、寄存器传输级以及行为级。算法级和系统级等不同层次上的功耗优化的理论和方法，并且对在各个层次上功耗优化所能达到的功耗改善的极限以及可改进的潜力作了进一步的探讨。

This paper analyzes and compares various low power design methods recently developed for CMOS integrated circuits, and discusses in detail the corresponding theory and methods in circuit level, logic level, resigter transfer level and behavioral level, algorithmic level and system level, etc. Moreover, the limit of improvement for power optimization in each level and the potential for further improvement are also discussed.