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全数字接收机中一种基于并行流水线与快速FIR算法的插值滤波器结构及其实现 被引量：9

Structure of Interpolation Filter Based on Parallel Pipelining and Fast FIR Algorithm and Its Implementation for All Digital Receiver
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摘要 该文在对已有的拉格朗日立方插值滤波器Farrow结构进行分析和研究的基础上,使用了流水线技术和并行处理技术来提高滤波器的速度。在此基础上提出了基于快速FIR算法的结构,降低了并行的Farrow结构的复杂度。对该算法结构进行了仿真,并在FPGA上实现。分析结果表明,改进后的结构有更快的运行速度和更低的功耗。 The analysis and research are based on the existing Farrow structure of Lagrange interpolation filter. The pipelining and parallel processing technology are used to improve the speed of filter. On this basis,a new structure based on the fast FIR algorithm is proposed. It is used to reduce the complexity of the parallel Farrow structure. The structure is implemented for FPGA. The analysis results show that the structure has faster operational rate and lower power consumption.
作者 邓军 杨银堂
机构地区 西安电子科技大学微电子学院 西安电子科技大学电子工程学院
出处 《电子与信息学报》 EI CSCD 北大核心 2010年第9期2089-2094,共6页 Journal of Electronics & Information Technology
基金 国家自然科学基金(60466047)资助课题
关键词 全数字接收机 插值滤波器 FARROW结构 快速FIR算法 All-digital receiver Interpolation filter Farrow structure Fast FIR algorithm
分类号 TN914.4 [电子电信—通信与信息系统] TN713 [电子电信—电路与系统]
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参考文献10

  • 1Gardner F M.Interpolation in digital modems part I:fundamentals[J].IEEE Transactions on Communications,1993,41(3):501-507.
  • 2Erup L,Gardner F M,and Harris R A.Interpolation in digital modems part II:implementation and performance[J].IEEE Transactions on Communications,1993,41(6):1135-1141.
  • 3Merlino P and Abramo A.A fully pipelined architecture for the LOCO-I compression algorithm[J].IEEE Transactions on Very Large Scale Integration Systems,2009,17(7):967-971.
  • 4邓军,杨银堂.全数字接收机中一种低功耗插值滤波器结构及其VLSI实现[J].西安电子科技大学学报,2010,37(2):320-325. 被引量：4
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二级参考文献7

  • 1Gardner F M.Interpolation in Digital Modems Part I:Fundamentals[J].IEEE Trans on Comm,1993,41(3):501-507.
  • 2Erup L,Gardner F M,Harris R A.Interpolation in Digital Modems Part II:Implementation and Performance[J].IEEE Trans on Comm,1993,41(6):1135-1141.
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  • 4Polpo A,Pereira C A B.Reliability Nonparametric Bayesian Estimation in Parallel System[J].IEEE Trans on Reliability,2009,58(2):364-373.
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共引文献3

同被引文献53

引证文献9

二级引证文献30

电子与信息学报
2010年 第9期

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