二维离散小波变换高效低存储VLSI架构设计

VLSI architecture for 2-dimensional discrete wavelet transform with high performance and low memory

通过改进二维离散小波变换（2DDWT）的提升算法,提出一种高效的硬件架构,可省去行列模块间的转置缓存,减少片内存储器需求,并可利用同一2DDWT架构实现JPEG2000中的5/3和9/7变换。对于N×N的图像（N为图像宽度）,进行5/3变换仅需2N片内缓存,进行9/7变换仅需4N片内缓存,关键路径为一个乘法器的延时。与已有的2DDWT架构相比,本架构省去了行列模块间的转置缓存,并利用折叠技术和流水线技术降低了硬件开销,缩短了关键路径,有效提升了系统性能。

This paper proposed a new high-performance and memory-efficient 2D DWT architecture with the modified lifting algorithm. It could effectively reduce the memory requirement by eliminating the transposing buffer. For an N × N image,only required 2N internal buffer for 5 /3 DWT and required 4N for 9 /7 DWT to perform 2D DWT with the critical path of one multiplier delay. Compared with the 2D DWT architectures existed,the architecture eliminated the transposing buffer between the row processor and the column processor and also adopted the folding and the pipeline technique to reduce the hardware resource and shorten the critical path.