可配置FFT/DCT协处理器及其VLSI设计

Reconfigurable FFT/DCT Coprocessor and Its VLSI Design

针对不同长度的FFT/DCT运算需要不同基数的碟形单元,导致性能和面积难以达到较好的平衡的问题,提出一种新的FFT/DCT实现结构.该结构中,当N为8的整数幂的FFT/DCT时,采用面积效率高的混合基-2/22/23结构,否则将混合基-2/22/23配置为基-8结构,使其与运算效率高的混合基-2/4结构组合在一起进行运算.基于此结构并结合零判决自动旁路和精度自适应控制机制,实现了一种可配置的FFT/DCT协处理器.该协处理器在UMC0.13μm工艺下综合的电路面积为148 K个门单元,工作频率为200 MHz.实验结果表明,该协处理器在不牺牲面积的前提下,明显地改善了FFT/DCT的运算性能.

Fast Fourier transform/discrete cosine transform（FFT/DCT） of different lengths need to be implemented with various butterfly structures,it is therefore challenging to achieve the tradeoff between the performance and area.A new FFT/DCT structure is proposed to remedy this problem.When N is equal to 8n for N-point FFT,the area-efficient radix-2/22/23 structure is used.Otherwise the radix-2/22/23 structure is configured as a radix-8 structure,combined with performance-efficient radix-2/4 structure.Using zero-detecting and the precision adaptive mechanisms,one reconfigurable FFT/DCT coprocessor is implemented based on this structure.The coprocessor can run at 200 MHz with 148K logic gates in UMC 0.13 μm process.Experimental results show that the coprocessor can improve the FFT/DCT performance without area sacrifice.