低DNL的SAR型模数转换器的设计

Design of Low-DNL SAR ADC

保证DAC中元器件的精度、减小DNL误差是提高SAR ADC性能的关键。通过对SAR ADC内部DAC的结构进行综合分析,针对传统的C-R混合式结构中的集总电容阵列进行了优化设计。电容阵列由相同的非集总的单位电容组成,并通过数字逻辑的控制来实现对单位电容连接点的选择。验证结果证明设计有效,ENOB、SFDR和SINAD等参数都得到明显的提高,保证了SARADC的单调性,实现了低DNL的SAR型模数转换器的设计。

Reducing the DNL error and ensuring the precision of components are the keys to improve the performance of SAR ADC. Based on comprehensive analysis of the interior DAC structure of SAR ADC, the paper presents an innovative design aimed at the traditional lumped capacitors in the C-R mixed style structure. The new capacitor array is composed nonlumped capacitors with identical unit size. The design decides which node should be connected to the unit capacitor under the control of digital logic. The proposed design methods are validated by the simulation result with HSPICE. The parameters of ADC such as ENOB.SFDR and SINAD are improved much, which guarantees a monotonic transfer function and realizes the low DNL SAR- ADC.