FPGA配置芯片测试方法的研究与实现

Research and Implementation of the Testing for FPGA Configuration Devices

集成电路规模越来越大,测试难度也越来越高,边界扫描方法的提出降低了测试的复杂度,适合进行大规模集成电路的测试。介绍了边界扫描的概念和特点,研究了FPGA配置芯片测试方法,并在V93000测试系统上实现了配置芯片EPC2的边界扫描测试,给出了具体测试过程,符合IEEE1149.1边界扫描规范,为具有JTAG接口的元器件测试提供了依据。

The test of the integrate circuit is more and more difficult with increasing of the scale. The complexity of the test is lower because of the Boundary scan. Boundary scan is suitable for testing of large-scale integrate circuit. This paper introduces the conception and the characteristics of Boundary-scan and studies the approach of FPGA configuration device. Then, implements the Boundary-scan test of configuration device EPC2 based on V93000 system and gives the detail of the testing process which meets the IEEE1149.1 Boundary-scan standard. This paper provides an important warranty for the test of the circuit having JTAG interface.