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GPU加速的二值图连通域标记并行算法 被引量:9

GPU accelerated parallel labeling algorithm of connected-domains in binary images
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摘要 结合NVIDIA公司统一计算设备架构(CUDA)下的图形处理器(GPU)并行结构和硬件特点,提出了一种新的二值图像连通域标记并行算法,高速有效地标识出了二值图的连通域位置及大小,大幅缩减了标记时间耗费。该算法通过搜索邻域内最小标号值的像素点对连通域进行标记,各像素点处理顺序不分先后并且不相互依赖,因此可以并行执行。算法效率不受连通域形状及数量的影响,具有很好的鲁棒性。实验结果表明,该并行算法充分发挥了GPU并行处理能力,在处理高分辨率与多连通域图像时效率为一般CPU标记算法的300倍,比OpenCV的优化函数(CPU)效率高近17倍。 In combination of NVIDIA's Graphics Processing Unit (GPU) parallel architecture and hardware features under Compute Unified Device Architecture (CUDA) architecture, a new parallel labeling algorithm of connected domain was proposed for binary images. It effectively located the connected domain of the binary image and recorded its size at high speed, and significantly reduced the marking time. It recognized the connected domain through searching the minimum labeled pixel value in neighborhood. Because the processing sequence of each pixel is not in particular order and independent from each other, it can be dealt in parallel. The calculation efficiency of the algorithm is independent of the shapes and the quantity of the connected regions, and the algorithm has good robustness. The experimental resuhs show that the algorithm fully plays the parallel processing capability of GPU, and can get a more than 300 times speedup than general algorithm based on CPU and 17 times speedup than OpenCV function (CPU) in processing high-resolution images and multi-connected-domain images.
作者 覃方涛 房斌
出处 《计算机应用》 CSCD 北大核心 2010年第10期2774-2776,共3页 journal of Computer Applications
关键词 GPU加速 连通域标记 并行化 统一计算设备架构 8邻域 GPU acceleration connected-domain labeling parallelization Compute Unified Device Architecture (CUDA) 8-neighborhood
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  • 1章德伟,蒲晓蓉,章毅.基于Max-tree的连通区域标记新算法[J].计算机应用研究,2006,23(8):168-170. 被引量:10
  • 2徐利华,陈早生.二值图像中的游程编码区域标记[J].光电工程,2004,31(6):63-65. 被引量:31
  • 3宋晓丽,王庆.基于GPGPU的数字图像并行化预处理[J].计算机测量与控制,2009,17(6):1169-1171. 被引量:10
  • 4OWENS J D, HOUSTON M, LUEBKE D. GPU computing [ J]. Proceedings of the IEEE, 2008, 96(5) : 879 -897.
  • 5NVIDIA Corporation. CUDA programming guide 2.0 [ S/OL]. [2010 -01 -03]. http://www, nvidia, com.
  • 6NVIDIA CUDA [ EB/OL]. [2010 - 01 - 03]. http://forums. nvidia, com.
  • 7HALFHIL T R. Parallel processing with CUDA [ J/OL]. Microprocessor Report, 2008, 22(1) : 1 -8 (2008 -01 -28) [2010 -01 - 08]. http://www, nvidia, com/docs/IO/47906/220401 _Reprint. pdf.
  • 8NICKOLLS J. Scalable parallel programming with CUDA [ J]. ACM Queue, 2008, 6(2): 40-53.
  • 9H1RSCHBERG D S, CHANDRA A K, SARWATE D V. Computing connected components on parallel computers [ J]. Communications of the ACM, 1979, 22(8) : 461 -464.
  • 10HE LIFENG, CHAO YUYAN, SUZUKI K, et al. Fast connected- component labeling [ J]. Pattern Recognition, 2009, 42(9) : 1977 - 1987.

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