12位20MS/s流水线ADC的研制

Design and Implementation of a 12 Bit 20 MS/s Pipeline ADC

流水线结构是高速高精度ADC的首选。通过对流水线ADC的结构、MDAC电路进行了研究;提出新型采样保持开关;设计了12位20 MS/s采样率流水线ADC,并基于SMIC0.35μm混合CMOS工艺进行流片实现,测试结果表明,在测试仪器只有10位精度的情况下SFDR=65 dB,SNDR=56 dB,SNR=56.9 dB,ENOB=9.1 bit,最后对测试结果进行分析。

Pipelined architecture is the first choice for high-speed and high-resolution ADC. By studying the structure of pipelined ADC and multiplying DAC （MDAC）, a novel booth-trap sample and hold switch was presented and a 12 bit 20 MS/s pipelined ADC was designed. The prototype ADC was fabricated in SMIC 0.35 ~m mixed signal technology and demonstrates SFDR = 65 dB, SNDR = 56 dB, SNR = 56.9 dB, ENOS = 9.1 bit with the resolution of all the measure instruments are below 10 bits. At last, the measured results were analyzed.