低功耗10位100MHz流水线A/D转换器设计

Design of A/D Converter for Low Power 10 b 100MHz Pipeline

介绍了一个10位100 MHz,1.8 V的流水线结构模/数转换器(ADC),该ADC运用相邻级运算放大器共享技术和逐级电容缩减技术,可以大大减小芯片的功耗和面积。电路采用级联1个高性能前置采样保持单元和4个运放共享的1.5位/级MDAC,并采用栅压自举开关和动态比较器来缩减功耗。结果显示,在输入频率达到奈奎斯特频率范围内,整个ADC的有效位数始终高于9位。电路使用TSMC 0.18μm 1P6 M CMOS工艺,在100 MHz的采样频率下,功耗仅为45 mW。

An analog to digital converter （ADC） for 10 b 100 MHz l. 8 V CMOS pipeline is presented in this paper. A adjacent stage operational amplifier sharing technology and progressively reduced capacitance technology are adopted in the ADC, which can reduce the chip area and power dissipation greatly. The capacitor scaling approach is used for the same purpose. A high performance sample/hold unit and four gain-boosted amplifiers are employed in the circuit. The simulation result shows that the effective number of bits （ENOB） of ADC is higher than 9 b as the input frequencies is up to Nyquist rate at 50 MHz. When the 0.18 μm 1P6M CMOS process of TSMC is used for the circuit, the power disspation is only 45 mW at the sample frequency of 100 MHz.