帧长可配置Turbo码编译码器的设计与实现

Design and Implementation of Turbo Encoder and Decoder with Variable Frame Length

针对固定帧长Turbo码灵活性和适应性差的缺点,提出了一种帧长可配置的Turbo码编译码器的FPGA实现方案,可以由用户根据数字通信参数设计要求自行改变交织深度,以使译码性能与信息速率达到最佳平衡。采用"自上而下"的设计思想和"自下而上"的实现流程相结合的方法,对Turbo码编译码系统进行模块化设计,优化调试后下载配置到Xilinx公司的Virtex-2 Pro系列中。测试结果表明,该设计具有良好的移植性和通用性,为Turbo码在不同环境下的应用建立了统一平台。

For the poor flexibility and adaptability of Turbo codes with fixed frame length, an implementation of turbo encoder and decoder whose frame length can be configured is proposed based on FPGA. The interleaving depth can be changed freely by users according to the parameter request of digital communication, so that the decoding performance and data rate can achieve the best balance. The options of combining the top-down design thought and the bottom-up method are used. The Turbo encoding and decoding system adopts module design and programs down to Xilinx＇s Virtex - 2 Pro series after optimum debugging. Test results show that the design has good portability and versatility, and constitutes a uniform platform for the application of Turbo codes in different environments.