高速HART C8PSK位同步与均衡系统设计

The timing and equalizer structure design of high speed HART C8PSK

提出一种新的低功耗HART C8PSK位同步与均衡结构,其中位同步初始化使位同步快速稳定,减少位同步跟踪计算频率和所需信号采样,从而降低均衡器和插值器的计算频率。同时根据HART信道特点,提出一种新的基于CSD编码的均衡器结构,使每个采样点均衡运算功耗大幅降低。整个系统通过资源复用,大量节省硬件资源。通过分析和仿真表明,该结构不仅能大幅降低功耗,而且具有很好的抗噪声性能。

This paper presents a novel low power HART C8PSK timing and equalization structure. The timing synchronizer attains equilibrium state quickly by using timing initialization, and subsequently reduces work frequency and samples needed for the timing tracking. So interpolator and equalizer, which offer samples for synchronizer, can work in low frequency too. According to the characteristic of HART channel, a novel CSD coded preset equalizer structure is introduced to lower the power consumption of equalizer operation for one sample. The whole structure saves resources by reusing them. Analysis and simulation has shown that the structure we developed not only can reduce power consumption but also has good noise tolerance.