期刊文献+

用于WLAN接收机的流水线A/D转换器设计

Design of a Pipelined A/D Converter for WLAN Receiver
下载PDF
导出
摘要 为一款支持802.11a/b/g协议的WLAN芯片设计了接收机内部的流水线A/D转换器。采用运放共享技术,减少了一半的运算放大器,节省了芯片面积,并降低了功耗。该A/D转换器采样速率为40 MHz,设计精度为10位,使用HJTC 0.18μm 1P6M CMOS工艺流片并测试成功,当输入频率为1 MHz、无杂散动态范围为61.43 dB的正弦信号时,测得输出数字信号的无杂散动态范围为58.6 dB,信号与噪声谐波失真比为52.87 dB,有效位数为8.49位。 A pipelined A/D converter was designed for WLAN receiver IC which supports 802.11a/b/g standard protocol.In this circuit,the number of operational amplifiers was halved by using op-amp sharing technique,which saves die area and reduces power consumption.Fabricated in HJTC 180-nm 1-poly 6-metal CMOS technology,the A/D converter operates at a sampling rate of 40 MHz with 10-bit outputs.Test results showed that,for a 1 MHz signal with an SFDR of 61.5 dB,the A/D converter had an output signal with SFDR,SNDR and ENOB of 58.6 dB,52.87 dB and 8.49 bits,respectively.
出处 《微电子学》 CAS CSCD 北大核心 2010年第5期627-630,共4页 Microelectronics
关键词 A/D转换器 运放共享 WLAN接收机 A/D converter Op-amp sharing WLAN receiver
  • 相关文献

参考文献10

  • 1ABO A M, GRAY P R. A 1. 5-V, 10-h, 14. 3-MS/s CMOS pipeline analog-to-digital converter [J]. IEEE J Sol Sta Circ, 1999, 34(5): 599-606.
  • 2ANNEMA A J, NAUTA B, VAN LANGEVELDE R, et al. Analog circuits in ultra-deep-submicron CMOS [J]. IEEE J Sol Sta Circ, 2005, 40(1): 132- 143.
  • 3ARIAS J, BISBAL D, PABLO J S, et al. Low power pipelined ADC design for wireless LANs [C] // Design of Circuits and Integrated Systems. 2003:399- 404.
  • 4MEHR I, SINGER L. A 55-mW, 10-bit, 40-Msample/s Nyquist rate CMOS ADC [J]. IEEE J Sol Sta Circ, 2000, 35(3): 318-325.
  • 5LEWIS S H, GRAY P R. A pipelined 5-Msample/s 9- bit analog-to-digital converter [J]. IEEE J Sol Sta Circ, 1987, 22(12): 954-961.
  • 6彭云峰,严伟,陈华,周锋.一种新型高线性度MOS采样开关[J].微电子学,2006,36(6):774-777. 被引量:5
  • 7MIN B M, KIM P, BOWMAN F W, et al. A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC[J]. IEEE J Sol Sta Circ, 2003, 38(12): 2031-2039.
  • 8RAZAVI B. Design of analog CMOS integrated circuits [M]. International edition. Singapore: McGraw- Hill Book Co. Singapore, 2001: 100-369.
  • 9SUMANEN L, WALTARI M, HALONEN K A. A 10-bit 200-MS/s CMOS parallel pipeline A/D converter [J]. IEEEJ Sol Sta Circ, 2003, 36(7): 1048-1055.
  • 10KAMATH Y, MEYER R, GRAY P R. Relationship between frequency response and settling time of operational amplifier[J].IEEE J Sol Sta Circ, 1974, 9 (6) : 347-352.

二级参考文献6

  • 1Allen P E,Holberg D R,Razavi.CMOS Analog Circuit Design[M].New York:Holt,Rinehart and Winston,1987.
  • 2Todd L B,David H R,Daniel F K,et al.A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR[J].IEEE J Sol Sta Circ,1997,32(12):1896-1906.
  • 3Andrew M A,Paul R G.A 1.5-V 10-bit 14.3 MS/s CMOS pipeline analog-to-digital converter[J].IEEE J Sol Sta Circ,1999,34(5):599-606.
  • 4Dessouky M,Kaiser A.Input switch configuration suitable for rail-to-rail operation of switched opamp circuits[J].Elec Lett,1999,35(1):8-10.
  • 5Troutman P R.VLSI limitations from drain-induced barrier lowering[J].IEEE Trans Elec Dev,1979,26(4):461-469.
  • 6Sze S M.Physics of Semiconductor Devices[M].New York:John Wiley & Sons,1981.

共引文献4

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部