摘要
为一款支持802.11a/b/g协议的WLAN芯片设计了接收机内部的流水线A/D转换器。采用运放共享技术,减少了一半的运算放大器,节省了芯片面积,并降低了功耗。该A/D转换器采样速率为40 MHz,设计精度为10位,使用HJTC 0.18μm 1P6M CMOS工艺流片并测试成功,当输入频率为1 MHz、无杂散动态范围为61.43 dB的正弦信号时,测得输出数字信号的无杂散动态范围为58.6 dB,信号与噪声谐波失真比为52.87 dB,有效位数为8.49位。
A pipelined A/D converter was designed for WLAN receiver IC which supports 802.11a/b/g standard protocol.In this circuit,the number of operational amplifiers was halved by using op-amp sharing technique,which saves die area and reduces power consumption.Fabricated in HJTC 180-nm 1-poly 6-metal CMOS technology,the A/D converter operates at a sampling rate of 40 MHz with 10-bit outputs.Test results showed that,for a 1 MHz signal with an SFDR of 61.5 dB,the A/D converter had an output signal with SFDR,SNDR and ENOB of 58.6 dB,52.87 dB and 8.49 bits,respectively.
出处
《微电子学》
CAS
CSCD
北大核心
2010年第5期627-630,共4页
Microelectronics