低功耗10位30MS/s流水线A/D转换器

A Low Power 10-Bit 30MSPS Pipelined A/D Converter

基于0.18μm CMOS混合信号工艺,设计了一个低功耗10位30 MS/s流水线A/D转换器。通过优化各级采样电容和运放(OTA)偏置电流,以及使用动态比较器,大大降低了整体功耗。采用增益自举开关,以减少开关非线性;引入数字校正技术,以提高转换精度。当采样时钟频率为32 MHz、输入信号频率为16 MHz时,信噪失真比(SNDR)为59 dB,无杂散动态范围(SFDR)为71dB。ADC核心电路版图面积为0.64 mm2,功耗仅为32 mW。

A low power 10-bit 30 MS/s pipelined A/D converter was designed based on 0.18 μm CMOS mixed signal technology.In this circuit,low power was achieved by optimizing values of sampling capacitors and bias current of the OTA in each stage,together with the use of dynamic comparators.Bootstrapped switches were used to reduce the nonlinearity of switches.High resolution was realized by introducing digital calibration technology.Simulation results showed that the proposed ADC had an SNDR of 59 dB and an SFDR of 71 dB at 32 MS/s sampling rate for an input signal of 16 MHz.The ADC occupies a chip area of 0.64 mm2,and it consumes only 32 mW of power.