一种用于锁相环快速锁定的动态鉴频鉴相器

A Fast Acquisition Dynamic Phase/Frequency Detector for Phase-Locked Loops

设计了一种用于电荷泵锁相环(CPPLL)快速锁定的动态鉴频鉴相器(PFD)。该PFD采用传统结构,利用开关延时动态D触发器预充电,复位时间内输入时钟边沿未发生丢失,有效地消除了盲区。基于TSMC 0.18μm CMOS工艺,用Cadence Spectre对其进行仿真验证。结果显示,采用新型PFD的锁相环,其锁定速度提高40.3%,频率范围达1 MHz^2 GHz。

A new dynamic phase/frequency detector（PFD） was designed for phase-locked loop（PLL） to enable fast frequency acquisition.Based on conventional structure,the proposed PFD eliminates blind area by delaying pre-charge of the dynamic D-type flip-flop with switch,to prevent edge loss during reset time.Based on TSMC＇s 0.18 μm CMOS process,the circuit was simulated in Cadence Spectre.Simulation results indicated that the proposed PFD,which operated in the frequency range from 1 MHz to 2 GHz,accelerated lock acquisition of a test bench PLL by 40.3%.