期刊文献+

10位100MHz CMOS流水线A/D转换器

A 10-Bit 100MHz CMOS Pipelined A/D Converter
下载PDF
导出
摘要 介绍了一种10位100MS/s流水线A/D转换器的设计方法,采用增益提升技术,实现了增益为100dB和单位增益带宽为1.2 GHz的高性能跨导运算放大器。改进了系统的延时单元,能够准确地锁存输出信号,减少噪声的影响。仿真结果表明,整个系统的有效位数提高了0.5位。整个系统基于TSMC 0.18μm CMOS工艺进行仿真,结果表明,整个电路的各个工艺角在温度为-20℃~85℃下均能满足100 MHz采样率流水线A/D转换器的要求。 A 10-bit 100 MS/s CMOS pipelined A/D converter was presented.By using gain boost technique and a new auxiliary operational amplifier,a high performance OTA with a DC gain of 100 dB and a GBW of 1.2 GHz was realized.An improved digital correction unit was employed,which can store output digital signal accurately,and alleviate effects of noise.It has been demonstrated that the effective number of bits of the system was improved by 0.5 bit.Simulation based on TSMC's 0.18 μm CMOS process showed that,at all process corners in the temperature range from-20 ℃ to 85 ℃,the proposed circuit could satisfy requirements for 10-bit 100 MHz pipelined ADC.
出处 《微电子学》 CAS CSCD 北大核心 2010年第5期662-666,共5页 Microelectronics
关键词 A/D转换器 采样保持电路 折叠共源共栅跨导运算放大器 增益提升 A/D converter Sample and hold circuit Folded cascode OTA Gain-boost
  • 相关文献

参考文献7

  • 1GUSTAVSSON M, WIKNER J J, TAN N-X N. CMOS data converters for communications [M]. New York: Kluwer Academic Publishers, 2002 : 61-86,235-247.
  • 2谭琚,闵昊.3.3伏100兆采样频率10比特流水线结构模数转换器的设计和低功耗实现[D].上海:复旦大学,2006:24-26.
  • 3LIU H-C,LEE Z-M,WU J-T. A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital back- ground calibration [J].IEEE J Sol Sta Circ, 2005, 40 (5) : 1047-1056.
  • 4CHIU Y, WOJCIECHOWSKI K. A gain-boosted 90-dB dynamic range fast settling OTA with 7. 8-mW power consumption [D]. Berkeley: University of California, 2000.
  • 5BULT K, GEELEN G. A fast-settling CMOS opamp for SC circuit with 90-dB DC gain [J]. IEEE J Sol Sta Circ, 1990, 25(6): 1379-1384.
  • 6SHAHRJERDI D, HEKMATSHOAR B,TALAIE M, et al. A fast settling, high DC gain, low power opamp design for high resolution, high speed A/D converters [C] /// Proc 15th Int Conf Microelec. 2003: 9-11.
  • 7孙超,李冬梅,刘力源,李福乐.14位20MS/sCMOS流水线A/D转换器[J].微电子学,2008,38(3):320-325. 被引量:2

二级参考文献4

  • 1LIU H-C, LEE Z-M, WU J-T. A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration [J]. IEEE J Sol Sta Circ, 2005, 40(5): 1047-1056.
  • 2BULT K, GEELEN G. A fast-settling CMOS op amp for SC circuits with 90-dB DC gain[J]. IEEE J Sol Sta Circ, 1990, 25(6): 1379-1384.
  • 3SUMANEN L, WALTARI M, HAKKARAINEN V, et al. CMOS dynamic comparators for pipeline A/D converters [C] // Int Syrup Circ and Syst. Arizona, USA. 2002: 157-160.
  • 4STEENSGAARD J, Bootstrapped low voltage analog switches [C]//Int Symp Circ and Syst. Orlando, F1, USA. 1999, Vol. 2: 29-32.

共引文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部