摘要
在高速视频系统中,信号完整性问题及互连延迟引起的时序偏移和紊乱可能导致设计失败,尤其是随着系统时钟频率的提高,数据的有效读写时间窗口越来越小,若要得到可靠的读写数据,需要进行精确的时序计算和分析。文章详细推导了系统时序所满足的约束条件,描述了如何通过仿真来指导实际布线,并举例说明了在实际系统布线中约束规则的设置。
In high-speed video system,timing skew and disorder caused by signal integrity issue and interconnection delay may lead to failure of the design.With increasing system clock frequency,the data valid window of time for reading and writing is getting smaller.It's necessary to perform a precise timing calculation and analysis to get a reliable reading and writing of data.This paper demonstrates constraint conditions that system timing should follow in detail,and describes simulation for guidance to practical wiring.Setting of constraint rules in actual system was also illustrated.
出处
《微电子学》
CAS
CSCD
北大核心
2010年第5期680-683,688,共5页
Microelectronics
基金
国家自然科学基金资助项目(50975019)
关键词
高速视频系统
信号完整性
时序分析
High-speed video system
Signal Integrity
Timing analysis