摘要
提出了一类有限域上的非二元准循环低密度校验(QC-LDPC)码。其校验矩阵具有特殊的结构,既可以用来构造规则码,也可以用来构造非规则码;特别的,通过优化重量为2的列的域元素选取,避免了低码重码字,改善了码的距离特性。针对此类码,提出了一种有效的编码算法,可采用简单的移位寄存器电路实现。复杂度分析表明这是一类线性时间可编的码,而且存储消耗很低。利用所提出的构造方法,在不同的域上构造了4个码。仿真结果表明,与高阶调制相结合,这些码展现出接近Shannon限的性能。
A class of nonbinary quasi-cyclic low-density parity-check（QC-LDPC） codes is presented.The special structure of the parity-check matrix allows the construction of both regular and irregular codes;in particular,low-weight codewords are avoided by optimizing the choices of field elements in weight-2 columns,thus improving the distance property.An efficient encoding algorithm for this class of codes is proposed,which can be implemented through simple shift-register circuits.Complexity analysis shows that they are a class of linear-time encodable codes with very low storage consumptions.Four codes are constructed over different fields using the proposed method.Simulation results show that when combined with higher-order modulation,these codes perform close to the Shannon limits.
出处
《电子科技大学学报》
EI
CAS
CSCD
北大核心
2010年第5期725-730,共6页
Journal of University of Electronic Science and Technology of China
基金
高等学校学科创新引智基地项目(B08038)
中央高校基本科研业务费专项资金(3Y10000901017)
国家973项目(2010CB328300)
关键词
有效编码
低密度校验码
非二元
准循环
SHANNON限
efficient encoding
low-density parity-check（LDPC） code
nonbinary
quasi-cyclic（QC）
Shannon limit
