宽带数字信道化并行结构及FPGA实现

Wideband Digital Channelized Parallel Architecture and Its FPGA Implementation

针对宽带数字信道化接收实时处理问题,提出了一种基于多相DFT滤波器组展开的并行结构。该结构从多处理器并行工作和系统工作频率上升两方面提高了信道化数据处理吞吐率。考虑到并行结构需要成倍资源消耗,对主要处理单元做出硬件资源优化,在单片FPGA上完成了2 Gsps数据流的实时处理,实现了瞬时覆盖带宽1 GHz、有效通道数128的宽带数字信道化,保证了宽带信号时域及频域的全覆盖。理论分析和硬件测试验证了结构的有效性。

Aimed at the real-time processing of the wideband digital channelizer,a parallel architecture is proposed from the unfolding transformation of the DFT polyphase filter banks.The architecture increases the channelized throughput by the simultaneous work of the multi-processors and the improvement of the system clock. The hardware resource optimization of the main processing units is presented to reduce the intensive area demands of the parallel architecture.A wideband digital channelized receiver with 2 Gsps throughput rate,1 GHz instantaneous frequency and 128 valid channels is implemented on a single FPGA chip,thus it guarantes the whole coverage in the time domain and the frequency domain of the wide-band signals.Theoretical analysis and hardware tests verify the effectiveness of the parallel architecture.