全数字低频锁相环的研究与应用

Study and Application of All Digital Low-Frequency Phase Locked Loop

采用嵌入式微机检测与控制技术开发了一种新型的低频锁相环控制系统;鉴相器采用时间数字转换器设计,克服了传统鉴相器存在鉴相死区的缺点;由于采用阻容式低频信号滤波器设计难度较大,采用计算机软件算术平均和滑动平均值滤波方案,解决了低频鉴相环路滤波器设计难题;该锁相环在GPS驯服晶振课题中应用,有效克服了GPS秒脉冲抖动噪声,结果表明,该锁相环结构简洁,控制参数调节方便,锁定后晶振频率准确度优于5E-11。

This paper develops a new type of low frequency phase locked loop with embedded microcomputer measure and control technology.The phase detector has been designed based on Time to Digital Converter without dead area.Because it is difficult to develop a low frequency filter using the usual resistor and capacitor,the numeric software is designed to filter the sample data,an adjacent averaging filter based on numeric algorithm and software processing is adopted.The DPLL is characteristic of its simple structure,flexible control method,high phase tracking precision and excellent loop performance,etc.It makes sure from the experiment results of the GPS disciplined OCXO frequency standard that the design method is correct,the accuracy of VCXO is about 5E-11.