支持突发传输的嵌入式误码仪设计和实现

Design of Embedded BER Tester Supporting Burst Transmission

灵活方便及低成本的误码测试仪是解决卫星通信系统大范围覆盖内各种终端性能测试的有效工具。分析了误码测试仪的使用需求,提出了一种基于现场可编程门阵列(FPGA)的嵌入式误码测试仪的设计方法。该方法实现简单、硬件资源占用非常少,采用VHDL语言编写,易于嵌入到多种卫星通信终端中,支持突发传输模式下的误码测试,便于终端的自检测试及辅助系统故障定位。

Flexible and low cost BER tester plays a key role in solving performance test of terminals in a satellite communication system which covers a wide area.After analyzing the requirement of embedded bit error ratio tester（BERT）,a designing method of embedded BER tester based on FPGA is put forward.This method has the advantages of being easy for implementation and occupying less resources.It＇s coded with VHDL,can be easily embedded in satellite communication terminal and support BER test in burst transmission mode,which is helpful for the terminal self-testing and the fault location of system.