基于CPLD的BCH码编/译码器的设计与实现

Implementation of BCH coder/ decoder based on CPLD

为提高BCH编/译码器系统性能,使硬件设计更具灵活性,提出了一种基于CPLD的BCH编/译码器实现方法。通过设计BCH(57,44,6)编/译码器,对BCH码的构造方法、BCH编/译码器进行了研究。论述了一种基于复杂可编程逻辑器件、采用模块化设计思想、利用VHDL硬件描述语言实现BCH编/译码器的方法;在QuartusⅡ软件环境下给出了BCH(57,44,6)编/译码器的仿真结果,并在CPLD器件上验证实现。仿真和实验都证明了这种方法的可行性和正确性。

To improve the BCH coder/decoder system performance and make hardware design more flexibility,a BCH coder/decoder design and method based on CPLD is presented.BCH code construction method and BCH coder/decoder are studied.An implementation of BCH coder/decoder that based on complex programmable logic devices,modular design and VHDL hardware description language is discussed.The simulation of BCH（57,44,6） coder/decoder in QuartusⅡ software platform is given and BCH coder/decoder in CPLD device are verified.The feasibility and validity of this approach is corroborated by simulation and experiment.