摘要
针对特大规模组合电路和全扫描设计电路提出了一种高速测试生成方法。该方法采用有限回溯测试模式产生方法生成测试码，采用ｎ（机器字长）个测试码并行的单故障传播方法模拟验证测试覆盖。测试生成与故障模拟为ｎ对１紧耦合集成方式。该方法运行１０个Ｂｅｎｃｈｍａｒｋ电路，取得了低测试长度、高故障覆盖、高效率的良好效果。
This paper presents a high speed test generation method specifically for upper large scale combination circuit(ULSCC) and full scan designed circuit. The method uses finite backtracking test pattern generation method to generate test code, and then simulates to validate the fault covering by means of parallel pattern single fault propagating method with n (machine word) test vectors. The mode for test generation and fault simulation is n to 1 tight coupled integrating mode. With testing the method with 10 ISCAS 85 benchmark circuits, the result is good for low test pattern length, high fault covering and high efficiency. [WT9.HZ〗
出处
《系统工程与电子技术》
EI
CSCD
1999年第6期1-5,共5页
Systems Engineering and Electronics
基金
国家自然科学基金
关键词
电路可靠性
测试技术
故障模拟
VLSI
组合电路
Full scan design\ Finite backtracking test pattern generation \ N to 1 tight coupled integrating mode\ Parallel pattern\ Single fault propagation \ Upper large scale combination circuit
