采用FPGA实现合并单元同步采样的方案

Synchronized sampling of merging unit with FPGA

为了提高数字化变电站模拟量采集的同步精度,提出一种利用现场可编程门阵列(FPGA)实现合并单元(MU)同步采样的方案。通过分析同步误差产生的原因,指出MU内部晶振误差是造成同步性能不确定的主要原因。根据MU同步采样的要求,将秒脉冲(PPS)接收和处理的过程分为2个功能模块:PPS的接收和等间隔采样,通过准确捕捉PPS脉冲沿和精确划分采样间隔来提高同步采样精度,并利用FPGA芯片的特点,对每个步骤分别进行补偿和处理,将其误差控制在一定的范围内。实验证明该方案能使MU同步精度达到1μs。

A synchronized sampling scheme of MU（Merging Unit） with FPGA （Field Programmable Gate Array） is proposed to improve the synchronization precision of analog sampling for digital substation. Analysis shows that the synchronization error is mainly caused by the crystal oscillator of MU. According to the requirement of MU synchronized sampling,the reception and processing of PPS（Pulse Per Second） is realized separately in two function modules：the PPS reception and the equal-interval sampling,which precisely detects the rising edge of PPS and divides the sampling interval to improve the synchronization precision. These two modules are compensated and treated separately with FPGA to control the error within a certain range. Experiments prove the synchronization accuracy reaches 1μs.