基于动态逻辑的MPRM电路低功耗优化设计

Low power optimization for MPRM circuits based on dynamic logic

n个输入变量的逻辑函数有3n种不同的MPRM(Mixed-Polarity Reed-Muller)表达式,其对应电路的功耗和面积不尽相同。本文通过对CMOS电路功耗和动态逻辑MPRM电路低功耗分解方法的分析,建立MPRM电路功耗和面积估计模型,而后提出一种基于动态逻辑的MPRM电路快速低功耗分解算法。在此基础上,针对中小规模和大规模MPRM电路,结合列表转换技术,分别将穷尽搜索算法和遗传算法应用于基于动态逻辑的MPRM电路低功耗优化设计中。通过对MCNC和ISCAS基准电路测试表明:与Boolean电路和FPRM(Fixed-Polarity Reed-Muller)电路相比,中小规模MPRM电路的功耗平均节省80.65%和50.98%,大规模MRPM电路的功耗平均节省69.17%和46.61%。

For an n-veriable logic function, power and area of 3n Mixed-Polarity Reed-Muller （MPRM） circuit implementations are different. Power and area estimation model of MPRM circuits are established by analyze of power consumptions of CMOS circuits and low power decompositions for MPRM circuits in dynamic logic. Then a fast algorithm of low power decomposition of dynamic logic-base MPRM circuits is proposed. Based on estimation models and decomposition algorithm, and combining tabular conversion techniques, exhaustive search algorithm is applied in low power optimization for mid-small scale MPRM circuits and genetic algorithm for large scale accordingly. Through several MCNC and ISCAS Benchmark tests, the results show that compared to Boolean circuits and Fixed-Polarity Reed-Muller （FPRM） circuits, mid-small scale MPRM circuits have achieved save power and area up to 80.65% and 50.98% on average, large scale MPRM circuits up to 80.65% and 50.98% on average, respectively.